The present application relates generally to an improved data processing apparatus and method and more specifically to an apparatus and method for predictive power gating.
In the field of microprocessor architectures, predicting certain key events ahead of their actual occurrence is a key problem. Such predictive algorithms are usually applied for the purposes of enhancing net performance. For example, predicting the direction and target of conditional branch instructions before they are actually executed helps performance, provided the misprediction rate is below a certain threshold. In the area of power management, a key problem is predicting the usage (activity) or lack thereof (inactivity) of a given resource ahead of the actual onset of such an event (where “event” means a minimum duration of activity or inactivity).
Prior approaches of predictive algorithms for use in computer architecture applications involve the use of table-lookup oriented state-based predictive algorithms. In such approaches, a prediction table (single or multi-level) indexed by some form of current processor state (e.g. the program counter), possibly in combination with history vectors that capture past behavior, is usually employed. In such existing art, the method employed is invariably that of predicting specific future events (e.g. branch direction and target) from past history and present processor state. Prior table-based predictive techniques have severe limitations when it comes to practical implementation in the particular problem domain of power gating, since the goal is to predict a “long enough” duration “idle sequence” of the resource being targeted for power gating. However, it is not enough to predict that a given unit will be idle in the next cycle or after a certain number of cycles. Adopting currently practiced state-based table-lookup oriented prediction, or even Markov-based state predictors would result in impractical hardware complexity.
Another problem in dynamic power-gating control is that such a controller unnecessarily works and consumes power, even if the net power savings is negative, because such a controller is not equipped with intelligence of when to turn off or on in response to monitored workload behavior and resource usage pattern within the microprocessor resources.
While power gating is a viable knob for leakage power management in microprocessors, current approaches only use a single level of control for predictive power gating. This control logic is usually implemented as a finite state machine controller that decides when to initiate power gating and when to disable it. In this class of power-gating control, an important parameter is the “breakeven point” (BEP), measured in processor cycles. This parameter is pre-computed to represent a value that means that the resource being power-gated needs to be OFF for at least BEP cycles in order for power gating to pay off; otherwise, if the resource is powered back on before BEP cycles, there is a net increase in consumed energy. The BEP value depends on the size of the macro that constitutes the resource being power-gated, as well as other factors that characterize the exact header or footer transistor design that is used as part of the gating circuitry. In such a single-level predictive power gating controller, there will be occasional mispredictions. That is, power gating will be initiated when it should not have been. In general, analysis shows that there could be cases where the overall power savings for a particular workload could turn out to be negative. The current class of single-level predictive algorithms cannot guarantee that the power-gating circuitry will always work for the intended purpose of effecting a net power gain.